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| INTEGRATED CIRCUITS DATA SHEET TDA9141 PAL/NTSC/SECAM decoder/sync processor Product specification File under Integrated Circuits, IC02 December 1992 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor FEATURES * Multistandard PAL, NTSC and SECAM * I2C-bus controlled * I2C-bus addresses can be selected by hardware * Alignment free * Few external components * Designed for use with baseband delay lines * Integrated video filters * CVBS or YC input with automatic detection * CVBS output * Vertical divider system * Two-level sandcastle signal * VA synchronization pulse (3-state) * HA synchronization pulse or clamping pulse CLP input/output * Line-locked clock output or stand-alone I2C-bus output port * Stand-alone I2C-bus input/output port * Colour matrix and fast YUV switch * Comb filter enable input/output with subcarrier frequency. GENERAL DESCRIPTION TDA9141 The TDA9141 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM decoder/sync processor. The TDA9141 has been designed for use with baseband chrominance delay lines, and has a combined subcarrier frequency/comb filter enable signal for communication with a PAL comb filter. The IC can process CVBS signals and Y/C input signals. The input signal is available on an output pin, in the event of a Y/C signal, it is added into a CVBS signal. The sync processor provides a two-level sandcastle, a horizontal pulse (CLP or HA pulse, bus selectable) and a vertical (VA) pulse. When the HA pulse is selected a line-locked clock (LLC) signal is available at the output port pin. A fast switch can select either the internal Y signal with the UV input signals, or YUV signals made of the RGB input signals. The RGB input signals can be clamped with either the internal or an external clamping signal (search tuning mode). Two pins with an input/output port and an output port of the I2C-bus are available. The I2C-bus address of the TDA9141 is hardware programmable. ORDERING INFORMATION EXTENDED TYPE NUMBER TDA9141 Note 1. SOT232-1; 1996 December 4. 32 PACKAGE PINS SDIL PIN POSITION MATERIAL plastic CODE SOT232(1) December 1992 2 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 December 1992 3 Fig.1 Block diagram. Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor QUICK REFERENCE DATA SYMBOL VCC ICC V26(p-p) V26(p-p) V22(p-p) V12 V14(p-p) V13(p-p) V10 V10 V11 V17 V16(p-p) supply current CVBS input voltage (peak-to-peak value) luminance input voltage (peak-to-peak value) chrominance burst input voltage (peak-to-peak value) luminance black-white output voltage U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) sandcastle blanking voltage level sandcastle clamping voltage level VA output voltage HA output voltage LLC output voltage amplitude (peak-to-peak value) 0 to 100% saturation standard colour bar standard colour bar top sync - white top sync - white PARAMETER positive supply voltage CONDITIONS MIN. 7.2 - - - - - - - - - - - - - - - - TYP. 8.0 45 1.0 1.0 0.3 1.0 1.33 1.05 2.5 4.5 5.0 5.0 500 0.7 5.0 200 5.0 TDA9141 MAX. 8.8 - - - - - - - - - - - - - - - - UNIT V mA V V V V V V V V V V mV V V mV V V21,20 19(p-p) RGB input voltage (peak-to-peak value) Vclamp I/O Vsub V15,16 clamping pulse input/output voltage subcarrier output voltage amplitude (peak-to-peak value) O port output voltage December 1992 4 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor PINNING SYMBOL -(R-Y) -(B-Y) Uin Vin SCL SDA VCC DEC DGND SC VA Yout Vout Uout I/O PORT PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TDA9141 DESCRIPTION chrominance output chrominance output chrominance U input chrominance voltage input serial clock input serial data input/output positive supply input digital supply decoupling digital ground sandcastle output vertical acquisition synchronization pulse luminance output chrominance V output chrominance U output input/output port output port/line-locked clock output clamping pulse/HA synchronization pulse input/output fast switch select input BLUE input GREEN input RED input I2C-bus address input (CVBS output) comb filter status input/output horizontal PLL filter chrominance input luminance/CVBS input analog ground filter reference decoupling colour PLL filter reference crystal input second crystal input SECAM reference decoupling O PORT/LLC 16 CLP/HA 17 F B G R ADDR (CVBS) Fscomb HPLL C Y/CVBS AGND FILTref CPLL XTAL Fig.2 Pin configuration. XTAL2 SECref 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 December 1992 5 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor FUNCTIONAL DESCRIPTION General The TDA9141 is an I2C-bus controlled, alignment-free PAL/NTSC/SECAM colour decoder/sync processor which has been designed for use with baseband chrominance delay lines. In the standard operating mode the I2C-bus address is 8A. If the address input is connected to the positive rail the address will change to 8E. Input switch WARNING: THE VOLTAGE ON THE CHROMINANCE PIN MUST NEVER EXCEED TDA9141 The standard identification circuit is a digital circuit without external components; the search loop is illustrated in Fig.3. The decoder (via the I2C-bus) can be forced to decode either SECAM or PAL/NTSC (but not PAL or NTSC). Crystal selection can also be forced. Information concerning which standard and which crystal have been selected and whether the colour killer is ON or OFF is provided by the read out. Using the forced-mode does not affect the search loop, it does, however, prevent the decoder from reaching or staying in an unwanted state. The identification circuit skips impossible standards (e.g. SECAM when no 4.4 MHz crystal is fitted) and illegal standards (e.g. is forced mode). To reduce the risk of wrong identification PAL has priority over SECAM (only line identification is used for SECAM). Integrated filters All filters, including the luminance delay line, are an integral part of the IC. The filters are gyrator-capacitor type filters. The resonant frequency of the filters is controlled by a circuit that uses the active crystal to tune the SECAM Cloche filter during the vertical flyback time. The remaining filters and the luminance delay line are matched to this filter. The filters can be switched to either 4.43 MHz, 4.28 MHz or 3.58 MHz irrespective of the frequency of the active crystal. The switching is controlled by the identification circuit. In YC mode the chrominance notch filter is bypassed, to preserve full signal bandwidth. For a CVBS signal the chrominance notch filter can be bypassed by I2C-bus selection of TB (trap bypass). The luminance delay line delivers the Y signal to the output 60 ns after the -(R-Y) and -(B-Y) signals have arrived at their outputs. 5.5 V. IF IT DOES THE IC ENTERS A TEST MODE. The TDA9141 has a two pin input for CVBS or YC signals which can be selected via the I2C-bus. The input selector also has a position in which it automatically detects whether a CVBS or YC signal is on the input. In this input selector position, standard identification first takes place on an added Y/CVBS and C input signal. After that, both chrominance signal input amplitudes are checked once and the input with the strongest chrominance burst signal is selected. The input switch status is read out by the I2C-bus via output bit YC. CVBS output In the standard operating mode with the I2C-bus address 8A, a CVBS output signal is available on the address pin, which represents either the CVBS input signal or the Y/C input signal, added into a CVBS signal RGB colour matrix WARNING: THE VOLTAGE ON THE UIN PIN MUST NEVER EXCEED 5.5 V. IF IT DOES THE IC ENTERS A TEST MODE. The TDA9141 has a colour matrix to convert RGB input signals into YUV signals. A fast switch, controlled by December 1992 the signal on pin F and enabled by the I2C-bus via EFS (enable fast switch), can select between these YUV signals and the YUV signals of the decoder. The Y signal is internally connected to the switch. The -(R-Y) and -(B-Y) output signals of the decoder have to first be delayed in external baseband chrominance delay lines. The outputs of the delay lines must be connected to the UV input pins. If the RGB signals are not synchronous with the selected decoder input signal, clamping of the RGB input signals is possible by I2C-bus selection of STM (search tuning mode), EFS and by feeding an external clamping signal to the CLP pin. Also in search tuning mode the VA output will be in a high impedance OFF-state. Standard identification The standards which the TDA9141 can decode are dependent on the choice of external crystals. If a 4.4 MHz and a 3.6 MHz crystal are used then SECAM, PAL 4.4/3.6 and NTSC 4.4/3.6 can be decoded. If two 3.6 MHz crystals are used then only PAL 3.6 and NTSC 3.6 can be decoded. Which 3.6 MHz standards can be decoded is dependent on the exact frequencies of the 3.6 MHz crystals. In an application where not all standards are required only one crystal is sufficient (in this instance the crystal must be connected to the reference crystal input (pin 30)). If a 4.4 MHz crystal is used it must always be connected to pin 30. Both crystals are used to provide a reference for the filters and the horizontal PLL, however, only the reference crystal is used to provide a reference for the SECAM demodulator. To enable the calibrating circuits to be adjusted exactly two bits from I2C-bus subaddress 00 are used to indicate which crystals are connected to the IC. 6 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor This compensates for the delay of the external chrominance delay lines. Colour decoder The PAL/NTSC demodulator employs an oscillator that can operate with either crystal (3.6 or 4.4 MHz). If the I2C-bus indicates that only one crystal is connected it will always connect to the crystal on the reference crystal input (pin 30). The Hue signal, which is adjustable via the I2C-bus, is gated during the burst for NTSC signals. The SECAM demodulator is an auto-calibrating PLL demodulator which has two references. The reference crystal, to force the PLL to the desired free-running frequency and the bandgap reference, to obtain the correct absolute value of the output signal. The VCO of the PLL is calibrated during each vertical blanking period, when the IC is in search mode or SECAM mode. If the reference crystal is not 4.4 MHz the decoder will not produce the correct SECAM signals. The frequency of the active crystal is fed to the Fscomb output, which can be connected to an external comb filter IC. The DC value on this pin contains the comb enable information. Comb enable is true when bus bit ECMB is HIGH. If ECMB is LOW, the subcarrier frequency is suppressed. The external comb filter can force the DC value of Fscomb LOW, as pin Fscomb also acts as input pin. In this event the subcarrier frequency is still present. If the DC value of Fscomb is HIGH, the input switch is always forced in Y/C mode, indicated by bus bit YC. Sync processor (1 loop) The main part of the sync circuit is a 432 x fH (6.75 MHz) oscillator the frequency of which is divided by 432 to lock the Phase 1 loop to the incoming signal. The time constant of the loop can be forced by the I2C-bus (fast or slow). If required the IC can select the time constant, depending on the noise content of the input signal and whether the loop is phase-locked or not (medium or slow). The free-running frequency of the oscillator is determined by a digital control circuit that is locked to the active crystal. When a power-on-reset pulse is detected the frequency of the oscillator is switched to a frequency greater than 6.75 MHz to protect the horizontal output transistor. The oscillator frequency is reset to 6.75 MHz when the crystal indication bits have been loaded into the IC. To ensure that this procedure does not fail it is absolutely necessary to send subaddress 00 before subaddress 01. Subaddress 00 contains the crystal indication bits and when subaddress 01 is received the line oscillator calibration will be initiated (for the start-up procedure after power-on reset detection see the I2C-bus protocol. The calibration is terminated when the oscillator frequency reaches 6.75 MHz. The oscillator is again calibrated when an out-of-lock condition with the input signal is detected by the coincidence detector. Again the calibration will be terminated when the oscillator frequency reaches 6.75 MHz. The Phase 1 loop can be opened using the I2C-bus. This is to facilitate On Screen Display (OSD) information. If there is no input signal or a very noisy input signal the phase 1 loop can be opened to provide a stable line frequency and thus a stable picture. TDA9141 The sync part also delivers a two-level sandcastle signal, which provides a combined horizontal and vertical blanking signal and a clamping pulse for the display section of the TV. Vertical divider system The vertical divider system has a fully integrated vertical sync separator. The divider can accommodate both 50 and 60 Hz systems; it can either locate the field frequency automatically or it can be forced to the desired system via the I2C-bus. A block diagram of the vertical divider system is illustrated in Fig.4. The divider system operates at twice the horizontal line frequency. The line counter receives enable pulses at this line frequency, thereby counting two pulses per line. A state diagram of the controller is illustrated in Fig.5. Because it is symmetrical only the right hand part will be described. Depending on the previously found field frequency, the controller will be in one of the COUNT states. When the line counter has counted 488 pulses (i.e. 244 lines of the video input signal) the controller will move to the next state depending on the output of the norm counter. This can be either NORM, NEAR_NORM or NO_NORM depending on the position of the vertical sync pulse in the previous fields. When the controller is in the NORM state it generates the vertical sync pulse (VSP) automatically and then, when the line counter is at LC = 626, moves to the WAIT state. In this condition it waits for the next pulse of the double line frequency signal and then moves to the COUNT state of the current field frequency. When the controller returns to the COUNT state the line counter will be reset half a line after the start of the vertical sync pulse of the video input signal. December 1992 7 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor When the controller is in the NEAR_NORM state it will move to the COUNT state if it detects the vertical sync pulse within the NEAR_NORM window (i.e. 622 < LC < 628). If no vertical sync pulse is detected, the controller will move back to the COUNT state when the line counter reaches LC = 628. The line counter will then be reset. When the controller is in the NO_NORM state it will move to the COUNT state when it detects a vertical sync pulse and reset the line counter. If a vertical sync pulse is not detected before LC = 722 (if the Phase 1 loop is locked in forced mode) it will move to the COUNT state and reset the line counter. If the Phase 1 loop is not locked the controller will move back to the COUNT state when LC = 628. The forced mode option keeps the controller in either the left-hand side (60 Hz) or the right-hand side (50 Hz) of the state diagram. Figure 6 illustrates the state diagram of the norm counter which is an up/down counter that counts up if it finds a vertical sync pulse within the selected window. In the NEAR_NORM and NORM states the first correct vertical sync pulse after one or more incorrect vertical sync pulses is processed as an incorrect pulse. This procedure prevents the system from staying in the NEAR_NORM or NORM state if the vertical sync pulse is correct in the first field and incorrect in the second field. If no vertical sync pulse is found in the selected window this will always result in a down pulse for the norm counter. TDA9141 Output port and input/output port Two stand-alone ports are available for external use. These ports are I2C-bus controlled, the output port by bus bit OPB and the input/output port by bus bit OPA. Bus bit OPA is an open-drain output, to enable input port functioning. The pin status is read out by bus via output bit IP. Sandcastle Figure 7 illustrates the timing of the acquisition sandcastle (ASC) and the VA pulse with respect to the input signal. The sandcastle signal is in accordance with the 2-level 5 V sandcastle format. An external vertical guard current can overrule the sink current to enable blanking purposes. December 1992 8 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 Fig.3 Search loop of the identification circuit. Fig.4 Block diagram of the vertical divider system. December 1992 9 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 Fig.5 State diagram of the vertical divider system. Fig.6 State diagram of the norm counter. December 1992 10 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 Fig.7 Acquisition sandcastle signal and VA pulse timing diagram. December 1992 11 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor Table 1 A6 1 Table 2 Inputs. MSB INA FORF EFS LCA INB FORS STM - TB OPA HU5 - ECMB OPB HU4 - FOA POC HU3 - FOB FM HU2 - XA SAF HU1 - Slave address (8A). A5 0 A4 0 A3 0 A2 1 A1 X A0 1 TDA9141 R/W X SUBADDRESS 00 01 02 03 Table 3 Outputs. LSB XB FRQF HU0 - ADDRESS I2C-bus protocol POR FSI YC SL IP SAK SBK FRQ If the address input is connected to the positive supply the address will change from 8A to 8E. Valid subaddresses = 00 to 0F Auto-increment mode available for subaddresses. Start-up procedure: read the status byte until POR = 0; send subaddress 00 with the crystal indicator bits (XA and XB) indicating that only one crystal is connected to the IC; wait for 250 ms; send subaddress 01; wait for at least 100 ms; set XA, XB to the actual crystal configuration. Each time before the data in the IC is refreshed, the status byte must be read. If POR = 1, then the above procedure must be carried out to restart the IC. Failure to stick to the above procedure may result in an incorrect line frequency after power-up or a power-dip. December 1992 12 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor INPUT SIGNALS Table 4 INA 0 0 1 Source select. INB 0 1 - CVBS YC auto CVBS/YC SOURCE Table 9 FORF 0 0 1 1 Forced field frequency. FORS 0 1 0 1 60 Hz 50 Hz TDA9141 FIELD FREQUENCY auto; 60 Hz if no lock auto; 50 Hz if no lock Table 5 TB 0 1 Trap bypass. CONDITION trap not bypassed trap bypassed Table 10 Output value I/O port. OPA 0 1 LOW HIGH CONDITION Table 6 Comb filter enable. CONDITION comb filter disabled comb filter enabled Table 11 Output value O port. OPB 0 1 LOW HIGH CONDITION ECMB 0 1 Table 7 FOA 0 0 1 Table 8 XA 0 0 1 1 Phase 1 time constant. FOB 0 1 - auto slow fast MODE Table 12 Phase 1 loop control. POC 0 1 CONDITION phase one loop closed phase one loop open Crystal indication. XB 0 1 0 1 CRYSTAL 2 x 3.6 MHz 1 x 3.6 MHz 1 x 4.4 MHz 3.6 and 4.4 MHz Table 13 Forced standard. FM 0 1 1 1 1 SAF - 0 0 1 1 FRQF - 0 1 0 1 STANDARD auto search PAL/NTSC second crystal PAL/NTSC reference crystal illegal SECAM reference crystal Note to table 13 1. If XA and XB indicate that only one crystal is connected to the IC and FM and FRQF force it to use the second crystal the colour will be switched off. December 1992 13 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor Table 14 Fast switch enable. EFS 0 1 CONDITION fast switch disabled fast switch enabled Table 19 Field frequency indication. FSI 0 1 50 Hz 60 Hz TDA9141 CONDITION Table 15 Search tuning mode. STM 0 1 CONDITION search tuning mode off search tuning mode on Table 20 Input switch mode. YC 0 1 YC mode CONDITION CVBS mode Table 16 Hue. FUNCTION hue ADDRESS HU5 to HU0 DIGITAL NUMBER 000000 = -45 111111 = +45 Table 21 Phase 1 lock indication. SL 0 1 not locked locked CONDITION Table 17 Line-locked clock active. LCA 0 1 CONDITION OPB/CLP mode LLC/HA mode Table 22 Input value I/O port. IP 0 1 LOW HIGH CONDITION OUTPUT SIGNALS Table 18 Power-on reset. POR 0 1 CONDITION normal mode power-down mode Table 23 Standard read-out. SAK 0 0 0 0 1 1 1 SBK 0 0 1 1 0 0 1 FRQ 0 1 0 1 0 1 - STANDARD PAL second crystal PAL reference crystal NTSC second crystal NTSC reference crystal illegal forced mode SECAM reference crystal colour off December 1992 14 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor LIMITING VALUES In accordance with the Absolute Maximum Rating System. (IEC134) SYMBOL VCC ICC Ptot Tstg Tamb ESD PARAMETER positive supply voltage supply current total power dissipation storage temperature operating ambient temperature electrostatic discharge (on all pins) Human body model Machine model Notes to the limiting values 1. Equivalent to discharging a 100 pF capacitor via a 1.5 k series resistor. 2. Equivalent to discharging a 200 pF capacitor via a 0 series resistor. THERMAL RESISTANCE SYMBOL Rth j-a PARAMETER from junction to ambient in free air note 1 note 2 -2000 -200 CONDITIONS - - - -55 -10 MIN. TDA9141 MAX. 8.8 60 530 +150 +65 +2000 +200 UNIT V mA mW C C V V THERMAL RESISTANCE 48 K/W December 1992 15 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor CHARACTERISTICS VCC = 8 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VCC ICC Ptot positive supply voltage supply current total power dissipation 7.2 - - 8.0 45 360 PARAMETER CONDITIONS MIN. TYP. TDA9141 MAX. UNIT 8.8 - - V mA mW Input switch Y/CVBS INPUT (PIN 26) V26(p-p) ZI V25(p-p) ZI V22(p-p) ZO Vtsl V8 input voltage (peak-to-peak value) input impedance top sync - white - 60 - 60 - - - - 1.0 - 0.3 - 1.0 - 2.8 1.43 - 0.43 - - 500 - - V k C INPUT (PIN 25) input burst voltage (peak-to-peak value) input impedance V k CVBS OUTPUT (PIN 22) ONLY ADDRESS 8A output voltage (peak-to-peak value) output impedance top sync voltage level top sync - white V V Bias generator (pin 8) digital supply voltage 5.0 V Subcarrier regeneration GENERAL CR catching range reference crystal 4.4 MHz reference crystal 3.6 MHz second crystal 3.6 MHz phase shift for 400 Hz deviation for 300 Hz deviation TC ZI temperature coefficient of oscillator input impedance reference crystal input second crystal input Vdep Vsub(p-p) Vcen Vcdis supply voltage dependency FSCOMB OUTPUT (PIN 23) subcarrier output amplitude (peak-to-peak value) comb enable voltage level comb disable voltage level CL = 15 pF 150 4.0 - 200 4.2 0.8 300 - 1.4 mV V V - - - 1.0 1.5 tbf - - - k k V 4.4 MHz 3.6 MHz - - - - - tbf 5 5 - deg deg Hz/K note 1 400 tbf 300 - - - - - - Hz Hz Hz December 1992 16 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL Isink RGND ACC PARAMETER minimum sink current to force output to comb disable level value of grounded resistor to force output to comb disable level CONDITIONS MIN. 0.4 0.4 TYP. - - MAX. 2.0 2.0 UNIT mA k ACC control range change of -(R-Y) and -(B-Y) signals over ACC range colour killer threshold PAL/NTSC SECAM kill - unkill hysteresis Demodulators -(R-Y) and -(B-Y) outputs (pins 1 and 2) ratio of -(R-Y) and -(B-Y) signals TC temperature coefficient of -(R-Y) and -(B-Y) amplitude spread of -(R-Y) and -(B-Y) ratio between standards V1 V2 B ZO Vdep V1(p-p) V2(p-p) V1,2(p-p) V1,2(p-p) VR(p-p) S/N V1(p-p) V2(p-p) fos S/N output level of -(R-Y) during blanking output level of -(B-Y) during blanking -3 dB bandwidth output impedance supply voltage dependency -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) crosstalk between -(R-Y) and -(B-Y) 8.8 MHz residue (peak-to-peak value) 7.2 MHz residue (peak-to-peak value) both outputs both outputs standard colour bar -20 - - - +5 1 dB dB - - - -25 -23 3 - - - dB dB dB 1.20 - -1 - - - - - 1.27 tbf - 2.0 2.0 1 - tbf 1.34 - +1 - - - 500 - 585 740 - 15 20 Hz/K dB V V MHz V PAL/NTSC DEMODULATOR standard colour bar standard colour bar 470 595 - - - - 46 - standard colour bar standard colour bar 0.94 1.19 - - 525 665 tbf - - - - 45 1.05 1.33 - 43 mV mV dB mV mV PAL DEMODULATOR H/2 ripple (peak-to-peak value) signal-to-noise ratio 50 - - 1.17 1.48 7 - mV dB NTSC DEMODULATOR hue phase shift -(R-Y) output voltage (peak-to-peak value) -(B-Y) output voltage (peak-to-peak value) black level offset signal-to-noise ratio deg SECAM DEMODULATOR V V kHz dB December 1992 17 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL Vres(p-p) fpole Vcal NL Filters TUNING Vtune td tuning voltage PARAMETER 7.8 to 9.4 MHz residue (peak-to-peak value) pole frequency of de-emphasis ratio of pole and zero frequency calibration voltage non linearity CONDITIONS MIN. - 77 - 3 - TYP. - 85 3 4 - MAX. 30 93 - 5 3 UNIT mV kHz V % 1.5 3.0 6.0 V LUMINANCE DELAY delay time PAL/NTSC SECAM B/W CHROMINANCE TRAP fO notch frequency fSC = 3.6 MHz fSC = 4.4 MHz SECAM YC mode; not active B bandwidth at -3 dB fSC = 3.6 MHz fSC = 4.4 MHz SECAM SUPP subcarrier suppression CHROMINANCE BANDPASS fres resonant frequency fSC = 3.6 MHz fSC = 4.4 MHz B bandwidth at -3 dB fSC = 3.6 MHz fSC = 4.4 MHz CLOCHE FILTER fres B Sync input VIDEO INPUT V26 sync pulse amplitude slicing level December 1992 18 Y/CVBS input 50 - 300 50 600 - mV % resonant frequency bandwidth at -3 dB SECAM SECAM 4.26 241 4.29 268 4.31 295 MHz kHz - - 1.4 1.7 - - MHz MHz - - 3.58 4.43 - - MHz MHz - - - 26 2.5 3.1 3.0 - - - - - MHz MHz MHz dB 3.53 4.37 4.23 3.58 4.43 4.29 3.63 4.49 4.35 MHz MHz MHz - - - 480 480 220 - - - ns ns ns Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL td S/N H td PARAMETER delay of sync pulse due to internal filter noise detector threshold level hysteresis delay between video signal and internally separated vertical sync pulse CONDITIONS MIN. 0.2 - - 12 TYP. 0.3 20 3 18.5 MAX. 0.4 - - 27 UNIT s dB dB s Horizontal section CLP OUTPUT (OPB/CLP MODE); HA OUTPUT (LLC/HA MODE) VOH VOL Isink Isource tW td td tW td FIRST LOOP f SVRR TC fCR fHR fO frequency deviation when not locked supply voltage ripple rejection temperature coefficient catching range holding range static phase shift - - - 625 - - - tbf tbf - - - 1.5 - - - 1.4 0.1 % V Hz/C Hz kHz s/kHz HIGH level output voltage LOW level output voltage sink current source current HA pulse width (32 LLC pulses) delay between middle of horizontal sync pulse and middle of HA delay between negative edge LLC pulse and positive edge HA pulse CLP pulse width delay between middle of horizontal sync pulse and start of CLP pulse note 2 CL = 15 pF 21 LLC pulses note 2 Isink = 2 mA 4.0 - 2 2 - 0.3 10 - 3.5 5.0 0.2 - - 4.7 0.45 20 3.1 3.7 5.5 0.4 - - - 0.6 40 - 3.9 V V mA mA s s ns s s LLC OUTPUT (LLC/HA MODE) output frequency 432fH 432fH VO(p-p) VO output amplitude (peak-to-peak value) DC output voltage level 50 Hz standard 60 Hz standard CL = 15 pF - - 0.25 - 6.75 6.80 - 2.5 - - - - MHz MHz V V Vertical section VERTICAL OSCILLATOR ffr free running frequency FORF = 1; divider ratio 628 FORF = 0; divider ratio 528 fLR frequency locking range - - 43 50 60 - - - 64 Hz Hz Hz December 1992 19 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL LR VA output VOH VOL Isink Isource tW PARAMETER divider locking range CONDITIONS MIN. 488 TYP. 625 MAX. 722 UNIT HIGH level output voltage LOW level output voltage sink current source current VA pulse width 50 Hz standard 60 Hz standard 4.0 - 2 2 - - - STM = 1 3 5.0 0.2 - - 160 192 32 - 5.5 0.4 - - - - - - V V mA mA s s s M td ZO V10 Isink Vbl Isource Iext tW td delay between start of vertical sync pulse and positive edge of VA pulse output impedance Sandcastle output (pin 10) zero level output voltage sink current 0 0.5 0.5 - 2.5 - - 10.2 6.7 1.0 - 3.0 - 3.0 - - V mA HORIZONTAL AND VERTICAL BLANKING blanking voltage level source current external current required to force the output to the blanking level horizontal blanking pulse width delay between start of horizontal blanking and start of clamping pulse 69 LLC pulses 45 LLC pulses 2.0 0.5 1.0 - - V mA mA s s CLAMPING PULSE Vclamp Isource tW td clamping voltage level source current pulse width delay between middle sync of input and start of clamping pulse 21 LLC pulses note 2 4.0 0.5 - 3.5 4.5 - 3.1 3.7 5.0 - - 3.9 V mA s s Colour matrix Gv gain from R to Y from G to Y from B to Y from R to Uout from G to Uout from B to Uout from R to Vout from G to Vout from B to Vout December 1992 20 - - - - - - - - - 0.43 0.84 0.16 0.43 0.84 1.27 1.00 0.84 0.16 - - - - - - - - - Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Output and input/output port O PORT (OPB/CLP MODE) VOH VOL Isink Isource VOH VOL Isink VIH VIL HIGH level output voltage LOW level output voltage sink current source current 4.0 - 100 100 - - 2 2.0 - 5.0 0.2 - - - 0.2 - - - 5.5 0.4 - - VSUP 0.4 - - 0.6 V V A A V V mA V V I/O PORT (OPB/CLP MODE) HIGH level output voltage LOW level output voltage sink current HIGH level input voltage LOW level input voltage YUV switches (note 3) RGB INPUTS (NOTE 3) VI(p-p) ZI VI(p-p) VI(p-p) ZI Y OUTPUT VO(p-p) ZO VO S/N U output voltage (peak-to-peak value) output impedance DC output voltage level signal-to-noise ratio top sync note 4; top sync-to-white - - - - - - - - sync locked - 1.43 - 2.5 tbf - 250 - - 1.90 1.50 250 - 10 V V dB input voltage (peak-to-peak value) input impedance note 4 - 3 - - 3 0.7 - 1.33 1.05 - 1.0 - 1.90 1.50 - V M UV INPUTS (NOTE 3) U input voltage (peak-to-peak value) V input voltage (peak-to-peak value) input impedance (both inputs) note 3 V V M UV OUTPUTS (NOTE 3) VO(p-p) VO(p-p) ZO VO GENERAL Vdiff difference between black levels of YUV outputs in RGB mode and YUV mode non-linearity bandwidth - mV U output voltage (peak-to-peak value) V output voltage (peak-to-peak value) output impedance (both outputs) DC output voltage level 1.33 1.05 - 2.7 V V V NL B any input to any output any input to any output - - - 7 5 - % MHz December 1992 21 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor TDA9141 SYMBOL CT PARAMETER crosstalk between RGB and UVin signals on UVout HIGH level input voltage LOW level input voltage gain from Uin to Uout from Vin to Vout CONDITIONS f = 0 to 5 MHz MIN. - TYP. - MAX. -50 UNIT dB FAST SWITCH SELECT INPUT (PIN 18) VIH VIL Gv RGB switched on UV switched on 0.9 0 - - between pin 18 and YUV - clamping no clamping 2.4 0 1.8 - STM = 1 3 - - 1 1 - - - 3.5 - - 3.0 0.5 - - 20 ns V V td VIH VIL tW Vos ZI switching delay INPUT CLAMP (PIN 17) HIGH level input voltage LOW level input voltage clamping pulse width clamping offset voltage on UV outputs input impedance 5.5 0.6 - 10 - V V s mV M Notes to the characteristics 1. All oscillator specifications are measured with the Philips crystal series 4322 143/144. If the spurious response of the reference crystal is less than -3 dB with respect to the fundamental frequency for a damping resistance of 1 k, oscillation at the fundamental frequency is guaranteed. The spurious response of the second crystal must be less than -3 dB with respect to the fundamental frequency for a damping resistance of 1.5 k. The catching and detuning range are measured for nominal crystal parameters. These are: load resonance frequency f0 (CL = 20 pF) = 4.433619 MHz, (second crystal: 3.579545 MHz) motional capacitance CM = 20.6 fF, (second crystal: 14.7 fF) parallel capacitance C0 = 5.5 pF, (second crystal: 4.5 pF). The actual load capacitance in the application should be CL = 18 pF to account for parasitic capacitances on and off chip. 2. This delay is caused by the low pass filter at the sync separator input. 3. The output signals of the demodulator are called -(R-Y) and -(B-Y). The colour difference input and output signals of the YUV switch are called UV signals. However, these signals do not have the amplitude correction factor of real UV signals. They are called UV signals and not -(R-Y) and -(B-Y) to prevent confusion between the colour difference signals of the demodulator and the colour difference signals of the YUV switch. 4. This value refers to signals including a sync pulse. For Y signals composed to the RGB inputs this output voltage is 30% lower, as there is no sync pulse on such signals. December 1992 22 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor QUALITY SPECIFICATION Quality level in accordance with URV 4-2-59/601. TEST AND APPLICATION INFORMATION TDA9141 Fig.8 Application diagram. Notes to figure 8 1. Pins 28 and 32 are sensitive to leakage current. 2. The analog and digital ground currents should be completely separated. 3. The decoupling capacitor connected between pins 8 and 9 must be placed as close to the IC as possible. December 1992 23 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil) TDA9141 SOT232-1 D seating plane ME A2 A L A1 c Z e b 32 17 b1 wM (e 1) MH pin 1 index E 1 16 0 5 scale 10 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION ISSUE DATE 92-11-17 95-02-04 December 1992 24 Philips Semiconductors Product specification PAL/NTSC/SECAM decoder/sync processor SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values TDA9141 with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I2C COMPONENTS Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011. December 1992 25 |
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